发明名称 SYSTEM CLOCK CONTROL SYSTEM
摘要 <p>PURPOSE:To attain ease of adjusting work and also to decrease a skew due to delay by consitituting the system that the phase of a clock signal and a stop signal is adjusted entirely within the machine cycle. CONSTITUTION:Although a true difference between two clock signals a, b is TD1, since the phase adjustment of TD2 is enough actually, the phase adjusting range of variable delay circuits 15-17 is smaller than the machine cycle time tau. Moreover, a phase difference TD3 between two stop signals c, d is separated into the two units of machine cycle time 2tau and a TD4 smaller than the tau, and in adjusting the phase difference 2tau by shift register 22 driven by the clock, the phase adjusting range of variable delay circuits 23-25 is decreased less than the machine cycle time tau.</p>
申请公布号 JPS60118922(A) 申请公布日期 1985.06.26
申请号 JP19830226336 申请日期 1983.11.30
申请人 FUJITSU KK 发明人 AZUMA ISAO;MUKAI MAKOTO;ITOU MIKIO
分类号 G06F1/10;G06F1/04 主分类号 G06F1/10
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