| 摘要 |
PURPOSE:To decrease number of signal lines by acquiring a data on a bus line in terms of time division in the leading and trailing timing of one control signal and outputting the data separately. CONSTITUTION:A control signal phi inputted to an input terminal 11 and its inverting signal are given respectively to latch circuits 2 and 3. Suppose that an address data A and other data D are given alternately on a bus line 1. The polarity of the control signal phi is inverted when the data is made stable while the kind of data is changed. The latch circuit 2 latches the data A at the trailing of the control signal phi and the data A is outputted always on an address line 9. The latch circuit 3 latches the data D similarly at the leading of the control signal phi and the data D other than the address data is outputted always on a data line 10. |
