| 摘要 |
PURPOSE:To reduce substrate-wafer resistance by forming the contact region of a substrate and a well into the desired U-shape as well as to enable to micro scopically form the contact region without having a latch-up by a method where in the gate electrode lead-out part of a transistor is extended to a contact region on the insulating layer which is formed including the gate electrode of the transistor. CONSTITUTION:The gate electrode lead-out part 2a of P-channel and N-channel MOS transistors 4 and 7 is extended to contact regions 9a and 10a on the insulating layer 13 which is formed including the gate electrode 1 of the transistors 4 and 7. In this case, the formation of the contact regions 9a and 10a is performed together with the MOS-FET 4 and 7 composed of a gate electrode 1 and S/D regions 3 and 6 and the MOS-FET 5 and 8 which are composed same as the MOS-FET 4 and 7 before the formation of the gate electrode lead- out part 2a. The gate electrode lead-out part 2a is formed by performing the overall growing of a polycrystalline Si, which is the same material as a gate electrode 1, for example, and the patterning thereof after the performance of overall coating of an SiO2 insulating layer 13 and the formation of the electrode window to be used for the insulating layer 13. |
