| 摘要 |
PURPOSE:To decrease the number of using flip-flops and also to reduce the power consumption by having proper combinations between switches and outputs of flip-flops constituting a ring counter and a shift register. CONSTITUTION:The output Q of each flip-flop constituting a multi-stage cascade circuit is connected to each input terminal of a switch S3, and the output side of the switch is supplied to a data input terminal of a flip-flop of a first stage of a circuit of a multi-stage cascade. In such a constitution a ring counter is obtained. A circuit is provided to delay the output of said ring counter by 1- (2m-1) bits, and this circuit consists of (n) units of flip-flops (n: 0 or a positive integer, n<=m) of a cascade structure. The ring counter output of the switch S3 is fed to a data input terminal of the flip-flop of the first stage to obtain a shift register. Therefore it is possible to extract a division output delayed by a desired number of bits out of an output terminal of a switch S4 by connecting the input and output terminals of the S4 to each other. |
