发明名称 SHIFT REGISTER MEMORY CONTROLLER
摘要 PURPOSE:To eliminate the transfer failure due to mismatching of transfer timing of data between a host system and a magnetic bubble storage element by providing a mechanism, which monitors always the number of data written in a first-in first-out memory (FiFo), to control transfer data. CONSTITUTION:A write permission signal control circuit 5 and a read permission signal control circuit 6 which count the number of data stored in a FiFo 1 and decide the counted value are provided, and a write permission signal WENBL and a read permission signal RENBL are outputted to a write means 3 and a read means 4 at a proper time. Thus, a proper control is performed to prevent overflow of a buffer in the FiFo 1 even in case of mismatching of data transfer timing between a host system H and a memory device, and the transfer failure is eliminated.
申请公布号 JPS60117487(A) 申请公布日期 1985.06.24
申请号 JP19830225648 申请日期 1983.11.30
申请人 FUJITSU KK 发明人 TANAKA KATSUNORI;IIDA TAKENORI;MINEMURA TOSHIMITSU
分类号 G11C11/14;G11C19/00 主分类号 G11C11/14
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