发明名称 SYSTEM FOR CONTROLLING COMMON BUS BUFFER
摘要 PURPOSE:To receive smoothly data from an I/O, by storing data from the I/O stored in a buffer memory through a common bus in a storage device in such a way that those having higher priorities of the I/O are preferentially stored. CONSTITUTION:Data on a common bus transferred from an I/O are written in a buffer memory by a writing circuit 13, but their addresses are detected and used by a priority detecting circuit 12 on a control bus. Priority information on the control bus is set in FFs 81-84 through a decoder 7. One having the highest priority is selected out of outputs of the FFs 81-84 by means of gates 91-94 and again converted into priority information (address of the buffer memory) by an encoder 10. Then the contents of the buffer memory of the address is read out and stored in a storage device 14 in the order of priority by a cycle steal. Therefore, data from the I/O can be received smoothly, even when an I/O to which high-speed processing of data is requested is connected.
申请公布号 JPS60117364(A) 申请公布日期 1985.06.24
申请号 JP19830225633 申请日期 1983.11.30
申请人 FUJITSU KK 发明人 SATOU MASAO;BABA YASUO;KABEMOTO AKIRA
分类号 G06F13/38;G06F13/12 主分类号 G06F13/38
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