| 摘要 |
PURPOSE:To obtain a gate array which is varied in the gate characteristic in a unit cell by providing a plurality of insulating layers for altering the inductance of the gate in the unit cell. CONSTITUTION:A ground plane layer 2 made, for example, of niob is formed on a silicon wafer 1, and the first insulating layer 3 made, for example, of SiO is deposited on the layer 2. Further, the second insulating layer 4 and the first gate 5 of, for example, Pb alloy are formed on the layer 3. The second gate 6 is formed on the layer 4. This is formed of a silicon wafer 1 added with the layer 4, the plane 2, the layers 3 and 4 and the second gate 6 of 5-layers in a structure having new gate characteristic. The thickness of the layer 4 is suitably designed to logically calculate as desired in the unit cell of the gate array. |
