COMMONLY USABLE PRESCALED TIMER FOR DATA PROCESSOR AND METHOD THEREOF

摘要

A data processor having an integral timer including a clock generator producing a specific frequency output comprises a counter chain having an input and output thereof for supplying a fixed frequency divide function. A programmable prescaler couples the clock generator output to the counter chain input for providing a predetermined divisor input to the counter chain. A postscaler operates in consonance with the programmable prescaler coupled to the counter chain output for providing a timer output compensated for the predetermined divisor input. In operation, the timer output has a frequency bearing a constant relationship to the clock generator output frequency independent of the predetermined divisor input of the programmable prescaler.