发明名称 |
METHOD AND APPARATUS FOR SELECTIVELY DISABLING POWER DOWN INSTRUCTION FOR DATA PROCESSOR |
摘要 |
A method for allowing the user of a data processor having a power-down instruction to selectively disable the power-down instruction. In the preferred circuit, the user stores a special code in a control register indicating that the power-down instruction is to be disabled. Upon a power-down instruction being subsequently executed, the processor is precluded by the code from turning off the oscillator which provides the system clocks. The method and circuit allows the code to be stored in the control register once and only once between system resets. |
申请公布号 |
JPS60116020(A) |
申请公布日期 |
1985.06.22 |
申请号 |
JP19840234013 |
申请日期 |
1984.11.06 |
申请人 |
MOTOROLA INC |
发明人 |
UENDERU RII RITORU;KENESU ROBAATO BAAKU |
分类号 |
H02J1/00;G06F1/04;G06F1/24;G06F1/26;G06F1/32;G06F9/30;G06F15/78 |
主分类号 |
H02J1/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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