发明名称 TESTING SYSTEM OF DATA PROCESSOR
摘要 PURPOSE:To enable an automatic testing using an instruction string including interruption in a data processing device in which plural arithmetic sections execute instructions in parallel, by comparing the result of execution of test instruction under non-preceding execution mode and preceding execution mode. CONSTITUTION:A test processor P0 transfers a group of test instructions M1 and a group of test data MD to the memory ME of a processor P1 to be tested. The result of execution of the group of test instructions under non-preceding execution mode is duplicated, and then the above-mentioned group of test instruction are executed under the proceding execution mode to obtain the result of execution of tested instruction. The test of hard ware under the preceding execution mode is made possible by comparing with the result of execution of tested instruction making a duplicated result of execution of instruction an expected value.
申请公布号 JPS60116047(A) 申请公布日期 1985.06.22
申请号 JP19830224687 申请日期 1983.11.29
申请人 FUJITSU KK 发明人 TONOI MASARU
分类号 G06F11/22 主分类号 G06F11/22
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