发明名称 DATA TRANSFERRING SYSTEM
摘要 PURPOSE:To eliminate failure in writing action by setting count value of a gap counter to include the worst value of access time of a main memory. CONSTITUTION:A data transfer control circuit 501 controls transmission and receiving of data request signals 100 and data reply signals 101 under the control of a gap counter 504, and takes written data sent from a channel device 4a through a bus 7 in a data buffer 502. Further, it sends out written data of the data buffer 502 to a bus 8 responding to a data request signal 200 from a magnetic disk device 6, and sends out a data reply signal 301. In the gap counter 504, the count up values are always compared with the value Y of a counter register 505 in which written data in the magnetic disk device 6 out of a gap length time TG are set not later and not earlier than timing of writing, and at the time of coincidence, output is obtained from a comparator 506.
申请公布号 JPS60116055(A) 申请公布日期 1985.06.22
申请号 JP19830223483 申请日期 1983.11.28
申请人 HITACHI SEISAKUSHO KK 发明人 SHIBATA YOSHIICHI
分类号 G06F13/12;G06F13/42;(IPC1-7):G06F13/12 主分类号 G06F13/12
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