| 摘要 |
PURPOSE:To reduce memory capacity by suppressing the execution of a microinstruction whose error is detected, and continuing the execution at another microprogram instruction of a microprogram stored in a control storage area. CONSTITUTION:When a parity checking circuit 4 detects a parity error during the execution of a microinstruction in an area A of the control storage CS1 and a detection line 400 goes up to 1, an inverter 56 outputs logic 0 to an execution indication signal line 503. Consequently, each output of a decoder 3 is allowed to pass through an AND gate 6 and the execution of a microinstruction containing a parity error read in a microinstruction register 2 is suppressed. Then, a microinstruction (B1) having the most significant digit bit set to 1 is supplied as an address specifying signal to the CS1 and a microinstruction read out of an area B is set in the microinstruction register 2. |
