| 摘要 |
PURPOSE:To shorten a cycle time, and to realize a high integration degree and a low power consumption by resetting automatically the previous circuits of an NOR gate of a row decoder and a column decoder, after an operation of the respective circuits have been ended. CONSTITUTION:A row address strobe signal falls, and a buffer 3 outputs non- inversion and inversion low address signals basing on an input address signal. As a result, a selective signal of a high level is impressed to a word line WL from a NOR gate of a row decoder, and a data read out of each memory cell MC is supplied to an input/output gate through a line BL and an amplifier 4. The buffer 3 and the NOR gate of the decoder 13 are reset automatically, respectively, after the operation has been ended. Subsequently, when a column address strobe signal falls, the read-out data from the cell MC is transferred to a bus DB basing on the selective signal from a NOR gate of a column decoder 14, in the same way. A buffer 7 and the NOR gate of the decoder 14 are reset automatically, after the operation has been ended.
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