| 摘要 |
PURPOSE:To reduce noise such as power supply noise by adopting the similar circuit constitution and time constant of an integration circuit to generate an automatic clear signal at throw-in of a power supply as those of a conventional circuit and adding a circuit setting noise immunity against power supply noise or the like to a desired level. CONSTITUTION:When an output Va reaches a circuit threshold voltage of an inverter 4, it is regarded as logical ''1'' and an output Vb is inverted and reaches ground level. An output Vc reaches a power supply VDD level at the same time. A transistor (TR)9 is not turned on so far and a positive feedback closed loop is not established, then the TR9 is turned on tna dnd the closed loop is formed. When the TR9 is turned on, since the TR9 is connected in parallel with a CMOS inverter 4, the circuit threshold voltage of the inverter 4 is shifted to a ground level, and even if the output Va being stable to a degree near the power supply voltage VDD is fluctuated because of power supply noise, when the level does not cross the circuit threshold voltage shifted to the ground level, the inverter 4 is not inverted. |
