发明名称 LAYOUT SYSTEM FOR SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
摘要 PURPOSE:To enable to automatically dispose a peripheral buffer circuit for input and output in a master slice LSI in an IC in a structure, wherein pads for input and output have been arranged on the peripheral parts of a semiconductor chip provided with internal logic circuits, by a method wherein the peripheral buffer circuit for input and output is provided on the inner sides of the pads for input and output through wiring regions. CONSTITUTION:Plural internal logic circuits 3 are formed in a sheet of Si substrate 1 and numerous pads 2 for input and output are provided on the peripheral parts of the substrate 1. A peripheral buffer circuit 4 for input and output is formed on the inner sides of the pads 2. At this time, wiring regions 5 for connecting the pads 2 and the circuit 4 is readily provided in between the pads 2 and the circuit 4. According to such a method, in a master slice LSI such as a gate array, it becomes possible to automatize the layout of the peripheral buffer circuit 4.
申请公布号 JPS60113943(A) 申请公布日期 1985.06.20
申请号 JP19830220608 申请日期 1983.11.25
申请人 HITACHI SEISAKUSHO KK 发明人 KAKIGI NOBUHIKO
分类号 H01L21/822;H01L21/82;H01L27/04;H01L27/118 主分类号 H01L21/822
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