| 摘要 |
PURPOSE:To reduce the circuit scale and power consumption of a Viterbi decoding circut sharing most of the hardware amount of an error correction circuit by adopting the constitution that a Viterbi decoding circuit is used mainly for extraction of error series and a circuit deciding the output is not provided into the Viterbi decoding circuit. CONSTITUTION:In taking a transmission efficiency of R=1/2 and a restricting length of K=3 as an example, a convolution coder 104 is provided to a transnission side 101 and the coder 104 consists of a shift register 105 and two exclusive OR circuits 106 and 107. When error series E<(1)>, E<(2)> are not applied on the midway of transmission, an output Q of a decoder 108 is equal to the original data series I fed to an input terminal 109 of a convolution coder 104. A circuit 121 extracting the error series consists of a recoder 111, synthesis circuits 112, 113 and a Viterbi decoder 116. SInce the input to the Viterbi decoding circuit 116 is a code subject to convolution coding of all ''0'' pattern, the most likelihood discriminating circuit 205 is saved in the Viterbi decoding circuit in Fig. and the final bit of the bus memory system connected to an ACS circuit corresponding to full ''0'' state is used as an output of the Viterbi decoding circuit, then the deterioration of the decoding gain is small. |
