| 摘要 |
PURPOSE:To obtain a frequency divider with setting whose internal state is invariable in a clock stop mode by defining the specific timing to apply setting or stop the clock and adding three transistors and an inverter. CONSTITUTION:When a set terminal 102 is set at a low level, transistors TR11 and 13 are turned off. A TR12 is controlled according to the potential of a terminal VA202. A feedback loop is formed since TR3 and 10 are off when a clock CL is kept at a low level. Thus an internal state, i.e., the state of a terminal VB17 has no change despite stoppage of the clock. Thus an action like that of a static frequency divider is obtained. Then the terminal 102 is set at a high level synchronously with the clock fall. Therefore the TR11 and 13 are turned on with the TR12 turned off respectively. Then an output terminal VC18 and the internal state (state of the terminal VB17) are set forcibly at a high level. |
