发明名称 DIGITAL SIGNAL PROCESSOR
摘要 For digital signal processing with a transversal filter having a (N-1) stage delay chain which is fed at its input with the digital signal to be processed and is provided with taps, subsum signals are stored which correspond to the N/w consecutive groups of, in each case Aw possible combinations of, in each case, w consecutive, A-value tapped signal elements, where the subsum signals are formed from tapped signal elements which are each assigned to a group and are evaluated in accordance with the relevant filter setting. During each delay stage, in accordance with the relevant N/w actual combinations tapped elements, the associated subsum signals are successively read from a memory and added to one another to form an output signal element. The subsum signals can be iteratively formed in that each of the successively-read subsum signals, combined with a correction value, forms a corrected subsum signal which is stored in place of the read subsum signal as a new subsum signal.
申请公布号 AU3663684(A) 申请公布日期 1985.06.20
申请号 AU19840036636 申请日期 1984.12.13
申请人 SIEMENS A.G. 发明人 HEINRICH SCHENK
分类号 H03H17/06;H03H17/00;H03H21/00;H04L25/03 主分类号 H03H17/06
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