| 摘要 |
PURPOSE:To convert to a signal with two-value, two-series stably by discriminating the point which exceeds a discrimination level of polarity and the opposite polarity immediately before the point. CONSTITUTION:The point which exceeds + and - discrimination levels +TH and -TH is discriminated by amplitude discriminators 2 and 3. In order to discriminate whether the opposite polarity immediately before this discrimination is 1 or 0, signals B and C before delaying by delay lines 4 and 5 of a delay time T0 are received by a clock input terminal, and signals E and D after delaying are also discriminated as zero by using flip-flops 6 and 7 which are inputted by a data input terminal. When it is not undershooted, inversion outputs of the flip-flops 6 and 7 become 1, and only the single part is outputted by AND gates 8 and 9.
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