发明名称 HYSTERESIS CIRCUIT
摘要 PURPOSE:To attain stable operation at a high speed and also in a wide source voltage range by constituting the titled circuit with the 2nd amplifier circuit amplifying inversely the output of the 1st amplifier circuit including an FET and the 3rd amplifier circuit amplifying inversely the output of the 2nd amplifier circuit and inputting the output of the 3rd amplifier circuit to the gate of the FET. CONSTITUTION:When an input voltage VIN transits from a low level to a high level with VIN<VT, since an FET22 is nonconductive, a potential V23 at an output terminal 23 of the 1st amplifier circuit 31 is kept to a power supply voltage VD being a high level and an output potential of amplifier circuits 32, 33 is kept respectively to a low level and a high level. When VIN>=VT, the FET22 starts conduction, and since the gate of a load FET12 is at high level, the potential V23 is not lowered voltage of the FET21 is at a low level, the on-resistance ratio of the FET21, 22 is large. Thus, even if the input level VIN is dropped, the V23 is not risen easily.
申请公布号 JPS60114021(A) 申请公布日期 1985.06.20
申请号 JP19830221608 申请日期 1983.11.25
申请人 NIPPON DENKI KK 发明人 UNO TAKASHI
分类号 H03K3/02;H03K3/3565 主分类号 H03K3/02
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