| 摘要 |
PURPOSE:To enable to improve the characteristics of a higher-withstand voltage transistor and a lower-withstand voltage transistor of the titled device as well as to enhance the integration degree of the device as well by a method wherein, when the higher-withstand voltage and lower-withstand voltage transistors are formed on the same substrate, the collector region of the higher-withstand voltage element is provided deeper than that of the lower-withstand voltage element by a selective epitaxial method and the higher-withstand voltage element is surrounded with a continuous lower-resistance collector layer and is isolated by the layer. CONSTITUTION:An N<+> type buried layer 22 and a P<+> type buried layer 23 are formed by diffusion in prescribed regions of the surface of a P type Si substrate 1, an N type layer 24 is epitaxially grown on the whole surface of the substrate 1, an etching is performed using an SiO2 film as a mask, and a recess 26 to intrude into the substrate 1 is formed in a part, where no buried layer exist, of the substrate 1. A P type diffusion layer 27, which is to become an isolation area, is provided on the inner side of the recess 26, parts of the N type epitaxial layer 24 exposing in the recess 26 are turned into a P type layer respectively, an N<+> type buried layer 28 is coated on the layer 27 and the interior of the recess 28 is filled with an N type epitaxial layer 29. After that, a P type isolation layer, by which a lower-withstand voltage element Tr2 is made to isolate, is formed on the layer 23 and each active region of the Tr2 is formed in the layer 24 having been formed on the layer 22, while each region of a higher-withstand element Tr1 is formed in the layer 29. |
