Circuit arrangement for decoding pulses from the drive pulse signal for a thyristor

摘要

In the case of a circuit arrangement for decoding the beginning and end of a firing phase and a check-back pulse on the serviceability of a thyristor from its drive pulse signal (E), in which the beginning of the firing phase is coded by a double pulse and the end of the firing phase is coded by a single pulse, it is intended to ensure that the supply power requirement for firing the thyristor is as low as possible in long firing phases in which renewal of the firing readiness is required. For this purpose, the drive pulse signal (E) is fed to a monostable element (2) and to two delay flipflops (3, 4). The delay flipflops (3, 4) can be triggered by the rising edge of the drive pulse signal, whereas the monostable element (2) is triggered by the falling edge of the drive pulse signal (E). The output of the monostable element (2) is connected to the delay input of the first delay flipflop (3), whereas its output is connected to the delay input of the second delay flipflop (4). Like outputs of the two delay flipflops (3, 4) are connected to an OR element (5), which is connected on the output side to the control terminal of the thyristor. The check-back pulse (R) for the serviceability of the thyristor can be derived from the rising edge of the output signal (A) of the OR element. <IMAGE>