| 摘要 |
<p>An integrated circuit shift register comprising regions (11,13,15 and 17) of n type semiconductor material formed by diffusion in a p- type epitaxy (3) formed on a substrate (5). Overlying each region (11,13,15 and 17) is a shallow diffusion of p type material (19,21,23 and 25), each provided with a projection (27,29,31 and 33) overlying the epitaxy material (3) between the regions (11,13,15 and 17) of n type semiconductor material. The regions of n type semiconductor material (11,13,15 and 17) each form common emitter and collector regions of adjacent bipolar lateral transistors in a series, the projections (27,29,31 and 33) form base contacts and the region of overlap between the shallow diffusions of p type material (19,21,23 and 25) and the regions of n type material (11,13,15 and 17) form a capacitor in the form of a reversed biased PN junction. A clocking pulse applied sequentially to the shallow diffusions of p type material causes movement through the shift register of data stored as voltages in the reverse biased PN junction. The clocking pulse sets up a potential gradient in the epitaxy (3) which restricts unwanted carrier injection into the substrate.</p> |
