发明名称 Method and circuit arrangement for synchronous detection
摘要 A digital signal comprising a plurality of data blocks each comprising a plurality of data words and a parity word is transmitted without a synchronous word or signal indicative of the boundary between two consecutive data blocks. The parity word comprises a plurality of bits each generated from bits of a corresponding row in the original data words in the data block. When receiving the digital signal, the digital signal is first stored in a memory and a plurality of sets of bits in each row is read out to provide parity checking. As a result of parity checking, absence of parity error will be detected in connection with a particular set of bits, and this particular set of bits in each row can be treated as a single row constituting the original data block. The stored digital signal will be read out and output on the basis of information of absence of parity error so that synchronism of data blocks can be established to accurately restore original analog information from the received digital signal having no synchronous word.
申请公布号 US4524445(A) 申请公布日期 1985.06.18
申请号 US19820434532 申请日期 1982.10.14
申请人 VICTOR COMPANY OF JAPAN, LIMITED 发明人 FUJII, YASUHIKO
分类号 H04L7/00;H04L7/04;(IPC1-7):G06F11/10;H04L7/02 主分类号 H04L7/00
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