| 摘要 |
PURPOSE:To reduce greatly the circuit scale and to facilitate an easy production of an IC device by decreasing greatly the number of delay circuits used for filters in comparison with the number of those delay circuits for approximation of series and at the same time setting the delay time of each delay circuit at the special and independent value. CONSTITUTION:A main filter F1 is provided with a circuit 10 which samples the instantaneous value of an analog input signal Ain sent from an input IN and synchronously with a clock having a fixed cycle, an A/D converter 12 which converts the sampled instantaneous value into an 8-bit parallel binary code, i.e., a digital input signal Din, two delay circuits Z<-1> and Z<-m> which produce three signals x0, x1 and xm having different delay times 0, DELTAtau and mDELTAtau from said signal Din, multipliers K0, K1 and Km which multiply prescribed coefficients k0, k1 and km respectively, two adders A1 and A2 which add signals k0x0, k1x1 and kmxm to each other, a gain correcting multiplier kb, etc.
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