Automatic adjustment of the amplitudes of plural-phase CCD clocking voltages

摘要

In a plural-level gate metallization CCD shift register the clocking voltages applied to the levels are automatically supplied differential offset biases to cause the potential wells to have uniform depth. The differential offset biases are developed responsive to the differences in the threshold voltages of insulated-gate field effect transistors integrated on the same semiconductor substrate as the CCD shift register so as to have their gate electrodes in the different levels of gate metallization.