| 摘要 |
PURPOSE:To obtain a complementary MOS memory circuit with less power consumption of DC current by constituting a titled memory in such a way that an output of the 1st complementary invertor is connected to either gate of the 1st and 2nd inter-connected complementary invertors. CONSTITUTION:Since one-shot signals phi1 and phi2 are low and high, respectively at the time of changing an address input Ai, a P-ch transistor Qp2, and an N-ch transistor QN3 are on; therefore changes in the address input Ai are transmitted to the interior. The changes in the address input Ai are latched by a flip-flop circuit constituted by inter-connection of complementary invertors 2 and 3. Then change in the address input Ai are detected, a generation circuit 11 of the one shot signal generates the complementary one shot signals phi1 and phi2. The P-ch transistor Qp2 and the N-ch transistor QN3 are turned off while the one-shot signals phi1 and phi2 are high and low, respectively, and therefore a DC supply current does not pass. |
