| 摘要 |
PURPOSE:To reduce the area of wiring areas and to simplify wiring steps by arranging rectangular auxiliary wirings formed in the same step as gate electrodes of MIS transistors which forms cells in an independent state in the same direction. CONSTITUTION:A plurality of rectangular auxiliary wirings H, H... formed in the same steps as gates G of both cell arrays 10, 10 are arranged in four rows in an independent state in a horizontal direction on wirings regions W, between basic cell rows 10, 10... which are different from a conventional device. Further, a plurality of rectangular auxiliary wirings I, I... formed in the same steps as gates G of the both cell rows 20, 20 are arranged in two rows in an independent state in a perpendicular direction on wirings regions V between input and output cell rows 20 and 20. In other words, when the gates G, G... of the cells 1..., 2... are formed, for example, of polysilicon, the wirings H, H..., I, I... of polysilicon are formed simultaneously, and the auxiliary wirings for the wirings are provided at the time of forming a master chip of a gate array. |
