发明名称 DECIMAL OPERATION PROCESSOR
摘要 PURPOSE:To execute operation with the minimum number of hardwares by providing the titled device with registers latching an operand consisting of a four- bit BCD code and a number to be operated respectively and registers latching a selector and its output, and reading out the contents of a ROM from these registers. CONSTITUTION:A bit string constituted of the outputs of the register 32 latching the operand expressed by a four-bit BCD code corresponding to one digit of data, the register 33 latching the operated number and the register 31 latching a carrying number and an initial value is connected to an address input of the ROM1. The ROM1 outputs four bits of the operated result in accordance with the input and four bits of a carried number by a selector 4. Consequently, the operation of decimal data consisting of the optional number of digits can be attained by the minimum number of hardwares without increasing the bit width of a data bus and the registers.
申请公布号 JPS60108932(A) 申请公布日期 1985.06.14
申请号 JP19830216101 申请日期 1983.11.18
申请人 HITACHI SEISAKUSHO KK 发明人 NISHIKAWA ATSUHIKO;HARA HIDEYUKI;WATANABE HIROSHI
分类号 G06F7/38;G06F7/48;G06F7/491;G06F7/494;G06F7/496;G06F7/525 主分类号 G06F7/38
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