发明名称 INTER-PROCESSOR INFORMATION TRANSFER CONTROL SYSTEM
摘要 PURPOSE:To reduce the load of transfer processing by connecting an additional bus between plural dispersed processors in addition to a C-bus and setting up transmission information such as the processed results by the processors and destination previously in local memory. CONSTITUTION:Local processors 6-8 are connected to a subscriber's circuit 2, a switch device 3 and trank devices 4, 5 of the like in a digital telephone set to constitute an inter-processor information transfer control system. Local memories 9-11 storing control information for respective circuits and devices are connected to respective processors 6-8. A master processor 12 having a control function and a common memory 14 enabled to access the whole processors 6-8, 12 are connected to respective processors 6-8 through the common C-bus. In addition to the C-bus, respective processors 6-8 are connected each other by an A-bus. The transmission information of the processed results of the processors 6-8 and destination are previously set up in the memories 9-11 to reduce the load of transfer processing.
申请公布号 JPS60108958(A) 申请公布日期 1985.06.14
申请号 JP19830217129 申请日期 1983.11.18
申请人 NIPPON DENSHIN DENWA KOSHA 发明人 YOSHIDA KENICHIROU
分类号 G06F12/00;G06F15/16;G06F15/173;H04Q3/545 主分类号 G06F12/00
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