发明名称 INTERRUPTION PROCESSING SYSTEM OF MICROCOMPUTER
摘要 PURPOSE:To improve the efficiency of interruption processing by adding a hardware to an interruption processing system of a microcomputer, and controlling a interruption input incapable of masking by a monitor. CONSTITUTION:If a non-maskable interruption input NMI incapable of masking is generated during the operation of the microcomputer 1, an NMI task starts an NMI mask flag control line 20-1 and sets up an NMI mask flag to prevent multiple NMI. Then, the NMI is processed and the NMI mask flag is reset by an NMI mask reset line 20-2. If it is necessary to start another task after the NMI processing, external interruption is set up by an interruption setting line 21-1, the whole registers are restored, then the NMI mask flag is reset. After completing the NMI processing, a monitor program executes external interruption processing, so that the NMI processing is recognized by the monitor program. Thus, the operating time of the monitor program is extremely shortened.
申请公布号 JPS60108935(A) 申请公布日期 1985.06.14
申请号 JP19830215941 申请日期 1983.11.18
申请人 OKI DENKI KOGYO KK 发明人 MASUDA MASAHARU
分类号 G06F9/48;G06F9/46 主分类号 G06F9/48
代理机构 代理人
主权项
地址