| 摘要 |
PURPOSE:To prevent data from being relinquished even write and read speed is slow by providing a clock generator for DRAM and supplying the clock to a refresh address counter when refresh is required. CONSTITUTION:The frequency of a clock generator 20 is selected to the maximum operating frequency by which the DRAM10 is operated. Write/read pulses PW, PR are supplied to a mode selection circuit 21 in addition to the clock CK and the write/read/refresh mode of the DRAM10 is formed selectively. When the refresh mode is selected from the circuit 21 together with the mode selection data DM, the clock CK is fed to a refresh address counter 23. Thus, in the refresh mode, the refresh address is selected and also each cell is refreshed by a pulse row and column ddresses RAS, CAS from the memory control circuit 22. Since the refresh is conducted when the pulses PW, PR do not exist in the mode cycle independently of the write and read speed, the refresh is always attained. |
