| 摘要 |
PURPOSE:To reduce errors contained in a reproducing data by processing and recording a digital signal inputted in a prescribed period, by the system clock of an apparatus, and also executing a multiple recording of the number of times corresponding to a sampling frequency of the input digital signal. CONSTITUTION:At the time of a reproducing operation, a tri-state circuit G11 and G16 become an active state, and also, in a period of a block of a control word, a tri-state circuit G12 becomes an active state. In the control word and a reproducing digital signal, only an effective data decided as an error flag is in a low level, namely, no error exists is written in a memory 51 and 61. As for the control word, that of the same is recorded extending over at least two blocks, and the digital signal is also recorded doubly when a frequency of an external clock CKW is lower than a frequency of a system clock CKS, therefore, almost all effective data can be reproduced together with an error correction by an error correcting code.
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