| 摘要 |
PURPOSE:To relieve the load of a CPU by connecting switchingly a memory between plural buses to an opposite bus to allow memories connected to opposite buses to transfer data thereby quickening data transfer. CONSTITUTION:In transferring a data stored in a memory 51 connected to a bus B1 to a memory 52 connected to a bus B2 under the control of a CPU2, a CPU1 gives a switching signal to a bus changeover circuit 41 at first. Thus, the memory 51 is cut-off from the B1 and connected to the bus B2. When the changeover of the bus is finished, the changeover of the bus is informed from the bus changeover circuit 41 to the opposite CPU2. The CPU2 accesses the memory 51 connected to the bus B2 of the own side, reads the stored data, allows the memory 52 connected to the bus B2 similarly to receive the transfer data and the data is written. |
