发明名称 COMMUNICATION CONTROL ERROR PROCESSING CIRCUIT
摘要 PURPOSE:To attain handling of a communication line only corresponding to an area in which a parity error is generated as a fault by providing a means displaying an error by a bit of an area on a line memory corresponding to the applicable communication line. CONSTITUTION:In reading a data from the line memory 6, the presence of an error is supervised by a parity check circuit 10; when an error takes place, the generation is stored in a line memory error storage circuit 11. An OR circuit 13 is provided to a route performing error display on the line memory 6. If an error takes place on a line bus 3 or the content of the line memory 6 is read, when the data error is detected by the parity check circuit 10, an error display bit E of an area of the communication line corresponding to any case is brought into ''1''. In this case, the control program conducts required processing by looking upon the said communication line only as faulted.
申请公布号 JPS60107159(A) 申请公布日期 1985.06.12
申请号 JP19830214476 申请日期 1983.11.15
申请人 FUJITSU KK 发明人 HOSHI FUMIO;KAWAMATA AKIO;TAKAHATA SHIYOUJI
分类号 H04L29/02;G06F11/10;G06F13/00 主分类号 H04L29/02
代理机构 代理人
主权项
地址