| 摘要 |
PURPOSE:To cut down the period of a test by a method wherein, in the semiconductor integrated circuit having a RAM back-up function and a test period detecting function, an information retention test for RAM and the detection of defect for ROM are performed simultaneously by giving a source voltage to the ROM too when a test is performed. CONSTITUTION:An OR type switch 21, having the back-up state reset command sent from the random gate part 17 of a switch 20 and the test command sent from a test port 16 as input, is provided and its output VDD3 is used as the power source of a ROM19. If a test command is sent to the OR type switch from the test port 16 when said circuit is going to be tested, the VDD3 is brought in the same voltage as a VDD1 even when no back-up state reset command is outputted from the random gate part 17. Therefore, an address is inputted to a ROM19 from an input port 14, and a RAM information retention test and a ROM defect detection can be performed simultaneously by sending out the output of the ROM19 from an output port 15. Thus, as the ROM defect detection can be performed while standing-by ready for the RAM information retention test, the test period can be reduced, and the cost of an LSI can be cut down.
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