Data processing system with processors having different processing speeds sharing a common bus

摘要

There is disclosed a data processing system comprising a plurality of processors having different processing speeds and connected with a synchronous common bus, the processors being able to access a common memory connected with the common bus. A high frequency master clock signal generating means is provided in common for the processors of the system and the respective processors can be operated with the associated different machine cycles determined in accordance with the corresponding different processing speeds by frequency-dividing the master clock signal. In addition, each processor can be operated with different machine cycles depending on its operations.