| 摘要 |
PURPOSE:To enable to cope with the formation of large scale structure of the titled semiconductor device as well as to enable to operate it at a high speed by a method wherein the bad effect caused by a parasitic MOS transistor effect is completely prevented. CONSTITUTION:The second insulating film 17 is coated on a metal film 15 in such a manner that a part or all of the metal film 15, on which a patterning has been performed, is left on the first interlayer insulating film 12 located on the surface of a semiconductor substrate 11 for the purpose of selective formation of a resistance region. As the electrostatic capacitance between the n type semiconductor part, which is located between resistor regions 13 and 14, and an upper layer metal wiring 16 can be made extremely small in size, the gate threshold voltage of a parasitic MOS transistor can be made larger in side. Besides, the generation of parasitic MOS transistor can be completely prevented by connecting the metal layer 15 to the highest potential which is used in this device.
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