| 摘要 |
PURPOSE:To shorten the maximum reading-out time by constituting in such a way that parasitic capacity of a data line is decreased when the memory cell away from a WD considerably affected due to delay of a word line is selected. CONSTITUTION:A data line is divided into two data lines D1 and D2, and an N- channel type field effect transistor Q' and a signal line S' are added. Sources QM1, QM2...QMN/2, a drain of the Q' and a precharge circuit PC are connected to the data line D2, and sources QMN/2+1, QMN/2+2...QMN, the drain of the Q' and the data input circuit IO are connected to the data line D1. A lateral traveling decoder CD' is connected to S1, S2...Sn and S', and a gate of the drain of the Q' is connected to the S'. As a result, when a memory cell MC with a small delay of a word line D is selected, it is permitted for information reading from the memory cell to be delayed; therefore the maximum value of reading time of an integrated memory circuit can be made smaller.
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