| 摘要 |
In a microprocessor system, data stored in a protected memory (12) within the same housing as the microprocessor (10) are secured by enabling access to the contents of the memory in response to an instruction only if the instruction was previously fetched from the memory (12). Protection circuitry (14) comprises a decoder (22, 24) responsive to the output of a status register in the microprocessor to operate a status signal when the microprocessor is in an instruction fetch machine cycle. The status signal is stored (26) until the protected memory (12) is selected by the microprocessor (10). Access to data in the protected memory (12) is enabled only if the status signal is stored during memory select or the microprocessor is in an I/O machine cycle for communication with a peripheral. In addition, voltage controlled switches within the housing place the bus in a HALT state during memory select unless the microprocessor is in an I/O machine cycle. The protection circuitry (14) is disabled by a fuse (36) within the housing for memory content verification. Following verification, the fuse (36) is blown to secure the memory (12).
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