| 摘要 |
PURPOSE:To hold the shortest bit length specified by the modulation/demodulation rule even at a connecting point betweena data and a synchronizing signal by inserting an excess coupling bit between the data and the synchronizing signal. CONSTITUTION:A data input signal S1 is subject to MFM modulation by an MFM modulation circuit 11, from which an MFM mudulation data S3 ending 01 is generated. A data flag S2 represented by ''1'' for a data area is inputted to the circuit 11, a bit deciding circuit 12 and a synchronism pattern generating circuit 14, the circuit 12 decides the state of the final clock bit from a flag S2 and a data S3, a control signal S4 corresponding whether the state is ''0'' or ''1'' is generated and fed to a coupling bit generating circuit 13. The circuit 13 generates a coupling bit S5 of ''1'' or ''0'' with an interval of 0.5T depeding whether signal S4 is ''1'' or ''0'' just after the data. The circuit 14 generates a synchronizing signal of 0011...0111 in succession to the bit S5 on the basis of the flag S2. An adder 15 couples the bit S5 and the signal S6 and supplies the result to an adder 16, the adder 16 couples the data S3 to the output of the adder 15 and outputs a signal S7 having a minimum bit length of an interval 1T between the data and the synchronizing signal. |
