| 摘要 |
PURPOSE:To output a clock disconnection signal for the period of a clock pulse number during disconnecting period by constituting the circuit with a monostable multivibrator, a delay circuit, an AND circuit and a set/reset flip-flop and using an output of the flip-flop as the clock disconnection signal. CONSTITUTION:The monostable multivibrator OM is constituted by connecting a capacitor CM and a resistor RM to terminals C, R. Since an output signal 5 is extacted from a terminal MQ', the signal is an inverting signal of an output signal 3 at a terminal MQ. The output signal 5, a signal 6 delaying the output signal 3 at the terminal MQ by a delay circuit DL and a clock signal 1 are inputted to the NAND gate NA. An output signal 7 and the clock signal 1 of the NAND gate NA are fed respectively to terminals S and R of a set/reset flip-flop SRF, the clock disconnection signal 8 is outputted from a terminal SRQ so as to display clock disconnection.
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