| 摘要 |
PURPOSE:To prevent the pulse width fluctuation of a digital logical signal due to the fluctuation of a mark rate in an input analog signal by providing a detection circuit obtaining a peak value independently of the non-inverting output and the inverting output of an amplifier circuit. CONSTITUTION:Detection circuits 3a, 3a obtaining a peak value independently from non-inverting and inverting outputs Vout, *Vout of the amplifier circuit 1 are provided. Through the constitution above, even if the mark rate is changed and the average level of a signal inputted to the detection circuit 3a is biased unidirectionally, as a matter of course, when the mark rate of the input analog signal is close to 50%, the other is biased oppositely so as to cancel the fluctuation, and the average value of the peak value detection voltage by the Vout, *Vout at all times is applied to an AGC voltage generating circuit 4, from which an AGC voltage is generated and the amplifier 1 is subject to gain control, then a proper gain control is executed even if the mark rate is changed from 50%. Then the Vout, *Vout being not deficient to the comparator circuit 2 are obtained and the pulse width of a digital logical signal obtained at the output of the circuit 2 is a signal waveform not affected by the change in the mark rate. |
