发明名称 DELAY CIRCUIT
摘要 PURPOSE:To obtain a delay circuit in which a maximum variable delay time is set optionally by providing a waveform shaping circuit having an output stage of open emitter and a comparator circuit comparing the output of waveform shaping circuit with a reference voltage in response to a desired delay time and obtaining an output pulse giving a desired delay time to the front edge or the rear edge to decrease the control voltage. CONSTITUTION:An IC1 is a comparator (or line receiver) whose output stage is open emitter and a constant current circuit CG and a capacitor C are connected to the output terminal. An IC2 is a comparator (or line receiver) with a high input impedance, an output of the comparator IC1 is connected to one input terminal E and a DC reference voltage Vref is applied to the other input terminal F. The constant current circuit CG can be a circuit comprising an operatonal amplifier IC, a transistor Q and a resistor R, the maximum variable delay time is set optionally and the delay time of the front edge and rear edge of an input pulse waveform is set independently.
申请公布号 JPS60103822(A) 申请公布日期 1985.06.08
申请号 JP19830210977 申请日期 1983.11.11
申请人 HITACHI SEISAKUSHO KK;HITACHI DENSHI ENGINEERING KK 发明人 NIIZAKI SHINYA;SAITOU TAKASHI;YAMAMURA HIDEHO;HAYASHI SHINICHI
分类号 H03K5/00;H03K5/13;H03K5/133 主分类号 H03K5/00
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