发明名称 Circuit arrangement for monitoring balanced lines
摘要 To monitor balanced lines via which binary signals are transmitted with signal levels which are inverted in relation to one another, the absolute value of the difference voltages on the two wires (L1, L2) of the balanced line is compared with a reference value. An error signal is emitted if the difference value is less than the reference value. The invention is intended for use primarily in digital bus systems. <IMAGE>
申请公布号 DE3342763(A1) 申请公布日期 1985.06.05
申请号 DE19833342763 申请日期 1983.11.25
申请人 SIEMENS AG 发明人 KNAUER,DETLEV,DIPL.-ING.;MUHR,ANDREAS,DIPL.-ING.
分类号 H04B3/46;H04L1/20;H04L25/08;(IPC1-7):H04B3/46 主分类号 H04B3/46
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