Starting from the objective of producing a clock generating device for printers with a positive and negative dead time compensation, in a clock generating device for printers with a pulse generating device constructed as an angle encoder and a pulse processing device arranged downstream containing a device for generating engine speed addresses with an engine speed counter and at least one memory which is designed as a PROM and arranged downstream of the device for generating engine speed addresses and the pulse generating device via an engine speed address data bus or an engine speed address data bus and at least one address conversion device, the engine speed counter is constructed as a decrementing counter.
