| 摘要 |
PURPOSE:To speed up vector operation process by providing a cache memory of high speed and large capacity in a vector operation unit, and at the same time, providing an exclusive address controller in a vector processor. CONSTITUTION:A cache memory 24d of high speed and large capacity that can store all operation data used for vector operation is provided in the vector operation unit 24. After writing operation data in the memory 24d from a main memory, operation data are supplied to an adder 24a and a multiplier 24b. Thus, operation data cn be supplied continuously conforming to the speed of processing. By providing the exclusive address controller 21 in the vector processor 20 and thereby controlling the unit 24 and adding special instruction, it becomes possible to process loop judging and condition judging by one machine cycle, and speed-up of the speed of vector operation process can be attained.
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