| 摘要 |
PURPOSE:To enable a central processor to transfer information at a high speed by controlling automatically a cache memory in response to the using factor of the cache memory. CONSTITUTION:A central processor 1 performs transfer of data with a memory 4 via a memory contro controller 2. The data requiring the high-speed processing among those stored to the memory 4 is also stored to a cache memory 33 of a cache memory part 3. Therefore the controller 2 performs transfer of data between the memory 33 and the processor 1. The part 3 contains a hit factor calculating part 31 which calculates in a fixed cycle the using frequency for read/write of data of the memory 33. The calculated value of the hit factor is supplied momentarily to a deciding part 32. The part 32 decides whether the calculated hit factor is higher than a desired level or not. Then the data of the memory 33 is controlled as a simulation mode when the calculated hit factor is less than the desired level. While the part 32 releases the simulation mode when the calculated hit factor becomes higher than the desired level during the control. |
