| 摘要 |
PURPOSE:To allow a device which is slow in access time to have access at optimum real time by providing a circuit which generates a prescribed time ready signal in response to an access signal from a CPU in a device to which access is made by the CPU. CONSTITUTION:An integrated circuit has a ready signal control circuit 2 built in a ROMIC1. The integrated circuit gives a lead signal and a chip select signal from a terminal 3 to a NOR circuit 4, leads out the output of said signals as data read-out control signals, inputs the signals into a NAND circuit 5 functioning as a control circuit which controls the ready signal conditions, and gives said signals to a shift register 7 through an inverter 6. Each bit output of the shift register 7 is selected by a selection circuit 9, and inputted into the NAND circuit 5 through an inverter 10. The integrated circuit changes connection of an intersecting point of the section circuit 9 and the output of the shift register 7 according to a basic clock supplied from the system, and controls the length of a ready signal. |
