| 摘要 |
PURPOSE:To mitigate software load in processing online real time by performing hardware-like assignment of a buffer surface of direct memory access (DMA). CONSTITUTION:A processor 61, a memory 2, a peripheral input/output device 3 which generates DMA demand 10, a logical operation circuit 4 which intervenes DMA demand 10 and controls the DMA, a group of registers 5, a group of flag 6, and an information control register 7 are connected to a bus O. In the information control register 7, a head address of memory within the control information during performance of the DMA, the number of transfer words, and action mode are set. A controller 8 loads to the information control register 7 the head address, the number of transfer words, and action mode of a memory 2 in the controlled information specified by a pair of registers among a group of registers 5 corresponding to a DMA area to which a flag is not set, by referring to the group of flags 6.
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